Instruments: MTCBitmap

Description Designed for SOC, DDR1,2,3 and SRAM testing, it provides you with a full image of your failing memory cells. The data can then be computed for device repair or process analysis.

The module works in conjunction with the MTD864 module which provides 64 channels at 800Mbps. The memory test algorithm is calculated by the HW APG embedded inside the MTD864 controller. It is applied to the DUT through the channel controllers which return the individual Pin/Fdata status.

The X,Y,Z, data and PFail are then carried up to the Bitmap controller which performs Read/Modify/Write cycles at Full speed into the Bitmap memory.


As displayed above, the controller and memory bank can be set for various memory width, depth and mode, allowing for all device to be characterized.

Key Features • 4 Gbit (Ready for 8 Gbit) memory bank working in RMW at tester full Speed
• Scalable layout allowing all memory type characterization:

• Scrambling memory for logical to physical address transformation
• Fail_0_only, Fail_1_only, differential mode
• Cumulated/Statistical mode: Counts the fail number per memory cell (16 or 8 bit)
• Data compression for memory read back
• Data post process for faster analysis

Applications • Automatic Test Equipment
• Memory repair
• Process analysis